The use of dynamic logic is an efficient way of increasing circuit speed and reducing die area of integrated circuitry. Many dynamic circuit schemes have been described which share common basic features. The basic dynamic gate, shown in FIG. 1, includes a logic structure whose output node 0 is precharged to V.sub.-- DD by a p-type transistor (the "precharge" transistor) and conditionally discharged to ground by an n-type transistor (the "evaluate" transistor). The precharge and evaluate transistors are connected to a single phase clock. During the precharge phase, the clock is low and the output node is precharged to V.sub.-- DD. At the completion of precharge phase, the clock goes high and the path to V.sub.-- DD is turned off while the path to ground is conditionally turned on. In this evaluate phase, depending on the state of the inputs, the output will either be at a high level or will be pulled down.
This dynamic logic is advantageous in that it generally requires less transistors than static logic. However, one major limitation of the basic dynamic CMOS gate as described above is that it cannot be cascaded. If two such basic gates are cascaded, as shown in FIG. 2, then during the precharge phase, the cascaded dynamic gates, G.sub.-- 1 and C.sub.-- 2 are precharged, i.e., dynamic output nodes O.sub.-- 1 and O.sub.-- 2 are precharged to V.sub.-- DD. During the evaluate phase, the output of the first gate G.sub.-- 1 will conditionally discharge depending on its inputs. However, some delay will be incurred due to the pull-down time of the gate. During this delay, all the inputs of next gate, G.sub.-- 2, remain precharged high and the evaluate transistor is also conducting (evaluate phase). Thus, the precharged output node O.sub.-- 2 can be discharged due to the delay of the previous stage, causing the output node O.sub.-- 2 to switch erroneously.
Domino logic, one example of which is illustrated in FIG. 3, overcomes the cascading problem of the basic dynamic logic structure. Domino logic allows a single clock to precharge and evaluate a cascade of dynamic logic blocks due to the static CMOS inverting buffer at the output of the dynamic logic gate. In cascaded domino logic blocks, each stage evaluates and causes the next stage to evaluate. During precharge, the output node of the dynamic gate is precharged high and the output of the inverting buffer is low. As subsequent domino logic stages are fed from this inverting buffer, their transistors will be turned off during the precharge phase. When the gate is evaluated, the output will conditionally discharge, causing the output of the inverting buffer to conditionally go high. Thus during the evaluate phase, the output of each dynamic gate in the cascade can make at most one transition, i.e., high to low. Hence, the output of the inverting buffer can only make a transition from low to high, enabling the cascading of dynamic logic stages.
Domino logic offers improvements over static logic in circuit area, and speed. But, since the evaluation logic of a domino gate, like that of a basic dynamic gate, has only N-type transistors, this logic must be non-inverting. Therefore, a need exists for a practical method and apparatus for designing logic which is free of inverters.